1. Field of the Invention
The present invention relates to a testing system, and particularly relates to a testing system sharing a register.
2. Description of the Prior Art
Conventionally, a BIST (Built-In Self Test) circuit is utilized to test an eSRAM (embedded SRAM). The data is output from the BIST circuit, stored to a SRAM to be test and then output, such that the SRAM can be determined if it has error or not. For the synchronization of the timing for the BIST circuit and the SRAM, a pipeline register will be provided at an output terminal of the SRAM, which will only be active while testing SRAM.
Besides the above-mentioned SRAM test, circuit function test will also be performed to the circuit (i.e. scan test). That is, a signal is transmitted from a logic circuit to another logic circuit, to test if any problem for the function of the signal transmitting path and the SRAM exists. In such case, a passby circuit is provided to isolate the SRAM and the logic circuit to increase test coverage of the logic circuit. Such passby circuit includes a register and another logic unit (ex. an XOR gate), and is only activated when the circuit function test is performed. Accordingly, the extra-provided passby circuit register and the pipeline register will increase a large amount of circuit areas.
Additionally, many inventions are provided to isolate the SRAM and the passby circuit. For example, U.S. Pat. No. 6,973,631 utilizes different passby circuits to isolate the SRAM and the passby circuit. However, such structure increases the area of the passby circuit. Also, a register is necessarily provided to the peripheral region of the SRAM to increase test coverage of the SRAM, thus the issue for large circuit area worsens. In view of above-mentioned description, prior art has the issue of large circuit area, in order to isolate the SRAM and the logic circuit.